1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device. In particular, this invention relates to a chemical mechanical polishing method (CMP) which is designed to be employed in the manufacture of a high-speed semiconductor device such as a memory LSI, a high-speed logic LSI, a system LSI, a memoryΩlogic hybrid LSI, etc.
2. Description of the Related Art
In recent years, the chemical mechanical polishing (CMP) method has been mainly employed as a planarization method to be used in the manufacturing process of a semiconductor device. As one of representative processes in which the CMP method is employed, there is known an element isolation technique called shallow trench isolation (STI). In the STI technique, a silicon nitride film is formed as a stopper film for CMP on the surface of a silicon substrate and then a shallow trench is formed in the silicon nitride film and in the silicon substrate, after which a silicon oxide film is deposited so as to fill the trench with the silicon oxide and then subjected to CMP to thereby remove a redundant portion of the silicon oxide film which is existed in regions other than the trench, thereby forming an element isolation region.
As for the polishing liquid to be employed in the CMP process for the STI, there is known to employ a polishing liquid containing cerium oxide as a polishing agent and an anionic polymer surfactant such as poly(ammonium carboxylate) as an additive (see for example, JP Patent No. 3278532 and JP-A 2005-142489).
Cerium oxide has a property that exhibits a higher polishing rate to a silicon oxide film than silica or alumina. On the other hand, the anionic polymer surfactant has a property that can be adsorbed on a silicon nitride film acting as a stopper film to suppress the polishing rate of the silicon nitride film, thereby enhancing the selective ratio of polishing rate between the silicon nitride film and the silicon oxide film. Further, this surfactant has also a property that enables to adsorb onto or desorb from the surface of cerium oxide particles depending on the polishing pressure, thereby making it possible to control the activity of the abrasive particles and hence to improve the polishing pressure dependency of polishing rate, thus enhancing the flatness of the polished surface.
However, due to the trend in recent years to further enhance the miniaturization of LSI in the vertical direction as well as in the lateral direction thereof, there have been raised the following outstanding problems in the CMP process for creating the STI. Namely, firstly, due to the increased miniaturization in lateral direction of LSI, minute flaws (scratches) on a silicon oxide film that may be caused to generate during the CMP and that may not arise any problem up to date are now having a bad effect on the electrical properties of a device, thereby reducing the yield. Secondly, due to the increased miniaturization in vertical direction of LSI, the thinning of the stopper film is inevitably promoted, whereby the suppression of the polishing rate of silicon nitride film would become insufficient, thereby making it impossible to secure a sufficient selective ratio between the silicon nitride film and the silicon oxide film. Thirdly, it is difficult to detect the termination of polishing especially on the occasion of applying a low polishing pressure.